The question arose today of alternative input/output architectures the ArcticLink III VX that aren’t explicitly listed.
First, let’s start by listing the 13 variants
I should also note that the interfaces which the customer requires are determined by their choice of processor and display–while we’ve address this ad nauseum before, it remains important to point out again before we get too far..
So getting back on point, the 13 I/O use cases are easy to identify by the chart…but what about a use case where a customer wants VEE and DPO, but has a MIPI 2-lane processor and a MIPI 3-lane display? We don’t have that specifically listed, so can QuickLogic address this bridging need?
The answer is yes. The VX3B2F is stated above as bridging MIPI 2-lane processor inputs and MIPI 4-lane display outputs. However, we can route the display data in such a way on our device that instead of sending 4 lanes out at half the speed of the 2 incoming MIPI lanes, we send out 3 lanes at 66% of the speed of the 2 incoming MIPI lanes. Doing so does not require new silicon, nor any significant changes — during set-up and calibration, we simply assist the customer with the correct initialization code for our VX3B2F device.
The next logical question might be could QuickLogic bridge MIPI 3-lane to MIPI 4-lane with a VX3B3B? Sure…provided we run across a processor or host system that only provides 3 MIPI lanes…and frankly, we have never seen that (today’s MIPI-enabled processors mostly support either 2 or 4 lanes).
Another question was specifically around QuickLogic’s ability to support a MIPI 2-lane to LVDS 2-channel bridge need. To note, this was not from a customer (potential or actual). While the VX5B3D could actually support that, I believe that this architecture would only have a single resolution that would it would be applicable to–the main reason being it would be a waste of power otherwise. Technical primer: as you increase the number of lanes or channels on I/O, you increase the ability to support higher resolutions, but at the penalty of increased power consumption. MIPI 2-lane, running at 1 Gbps (our maximum MIPI lane speed on the ArcticLink III VX CSSP, and generally the fastest MIPI lane speed supported by any processor or display), provides display resolution support up to and including 1366 x 768 at 60 frames per second (FPS). If the OEM wants to go to a higher resolution, it will require additional MIPI lanes. LVDS works the same way, with single channel speed display resolution support being limited up to an including 1280 x 720 (720p). Therefore, the only resolution in which a customer might use a MIPI 2-lane to LVDS 2-channel bridge would be 1366 x 768. Moving to a lower resolution than that allows the customer to use a lower power, single channel LVDS display (which is supported by QuickLogic’s VX5B1D). Increasing the resolution beyond 1366 x 768 will require more than 2 lanes of MIPI from the processor, which as we’ve mentioned above means 4 lane. That is, of course, easily handled by the VX5B3D MIPI 4-lane to LVDS 2-channel bridge.