As the final blog before we (OK, I) settle down for a long winters nap, I wanted to mention a few items about the size of the ArcticLink III VX device.

Yes, we’ve shrunk the device 44% from 6 x 6 mm to 4.5 x 4.5 mm.  This is true for all 13 variants of the device (a single package allows us manufacturing economies of scale).   The shrinking of the device is due to many factors, primarily:

• Process node shrink
• Optimization of VEE and DPO HD+ algorithms
• Elimination of fabric

So, although this is likely patently obvious to anyone familiar with semiconductors, we’ve moved away from our previous 180nm process node to a much smaller 65nm node (we aren’t going to get into specifics of where right now).  This smaller node allows us to pack much more per square millimeter than before, allowing for the device to be much smaller than it would have been on 180.  This process node shrink also is a big factor in the power consumption reductions we spoke about in our ArcticLink II vs ArcticLink III comparison earlier.

We spoke a bit in a previous blog about the VEE and DPO HD+ optimizations, specifically in the ‘streamlining of technology’ section, which you can read at the link above.

And finally, the elimination of fabric on this specific platform of parts is a huge space saver.

All of these lead to a much smaller die…and I’d be remiss if I overlooked the accomplishments of our various engineering teams in optimizing die space to cram as much as possible into every square millimeter (or should that be nanometer?) of the device.  Their dedication allowed us to make sure all 13 silicon variants are sized right for the market.

And with that, dear reader, ugly sweaters, egg nog, and fruit cakes are calling my name.  If we don’t speak, we’ll see you in 2012, with CES right around the corner!