During Uplinq last week, visitors to our booth were, among other things, given demonstrations of VEE and DPO.  One of the curious things that kept occurring was people trying to understand how we can reduce power with silicon.  I suppose for most techies, “adding silicon to reduce power” is in the vein of “jumbo shrimp” and “government intelligence” and other oxymoron’s– things that don’t belong together.

With DPO, adding silicon truly does reduce system power.  Our chip consumes power—that is certainly true.  So when in operation, VEE and DPO are absolutely pulling current from the battery.  However, as we reduce display power considerably, our chip power consumption is more than accounted for.   The power savings numbers we publish are real-world numbers on form factor systems, and absolutely include the power consumed by our chip.

You can actually add silicon and reduce power.   With QuickLogic CSSPs, of course…