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ArcticPro™ Ultra-Low Power Embedded FPGA (eFPGA) IP

Build Flexibility and Differentiation Into Your Next SoC

QuickLogic has been supplying FPGA-based products for consumer, industrial and mission-critical applications for nearly three decades. The company’s embedded FPGA (eFPGA) initiative offers SoC designers the flexibility to easily implement post-production changes, thus providing the benefit of hardware programmability to their end customers. Multiple chip variants can be created from a single mask set, enabling customization to address fragmented and/or rapidly evolving standards.


Benefits – ArcticPro eFPGA:
  • Efficient Architecture: high logic cell utilization
  • Fine-Grain Architecture – can implement multiple input functions in two independent LUT3s or one LUT4
  • Up to 8:1 mux & independent 2:1 mux
  • Flexible Flip Flop
  • Flip flop can be driven by logic in the cell
  • Flip flop can be used independently of the logic in the cell
  • Highly Routable Architecture
  • Reduces routing delays
  • Multi-drop routing for better routing resource utilization
  • Array sizes ranging from 8×8 logic cells up to 64×64 logic cells

Product Options – 65nm

Foundry Process Device Type Architecture Available Array Sizes # of RAM bits # of Logic Cells # Flip Flop&& # GPIO
TSMC 65nm LP SVT ArcticPro 32×32 73,728 (RAMFIFO) 1019 1019 (LC)
384 (IO)
128
GF 65nm LPE HVT, SVT ArcticPro 32×32 73,728 (RAMFIFO)
135,168 (ASSP)
1019 1019 (LC)
1019 (LC)
264 (IO)
88

Custom array sizes, process and device types available
&&22LC + PREIO register paths
**with die seal + scribe line

ArcticPro – 40nm

Foundry Process Metal Layers Available Array Sizes # of Logic Cells # Flip Flop # Interface signals&&
GF 40nm LP 5 32×32 1019 1019 (LC)
192 (IO)
64+768 (A2F%)
128+1536 (F2A%)
256 (DEF)
SMIC 40nm LL 5 32×32 1019 1019 (LC)
192 (IO)
64+768 (A2F%)
128+1536 (F2A%)
256 (DEF)
TSMC 40nm ULP 5 32×32 1019 1019 (LC)
192 (IO)
64+768 (A2F%)
128+1536 (F2A%)
256 (DEF)

Custom array sizes, process and device types available

Compiler Example Arrays

Available Array Sizes # of Logic Cells # Flip Flop&& # Interface signals&&
16×16 251 251 (LC)
96 (IO)
32+384 (A2F%)
64+768 (F2A%)
128 (DEF)
48×48 2283 2283 (LC)
288 (IO)
96+1152 (A2F%)
192+2304 (F2A%)
384 (DEF)

&&LC + PREIO register paths
%(reg) + (combinatorial)
*Based on APB 40MHz clock

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