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ArcticPro 2™ Embedded FPGA (eFPGA) IP for Hardware Acceleration

Increase Performance by Adding Reprogrammable Hardware Accelerators, Based on eFPGA, in Your Next SoC

QuickLogic has been supplying FPGA-based products for consumer, industrial and mission-critical applications for nearly three decades. The company’s embedded FPGA (eFPGA) initiative enables SoC designers to benefit from our experience and add flexibility to easily implement post-production changes, thus providing the benefit of hardware programmability to their end customers. Multiple chip variants can be created from a single mask set, enabling customization to address fragmented and/or rapidly evolving standards.


ArcticPro 2 eFPGA

  • High-performance architecture for low power applications
  • Super Logic Cell (SLC) clusters 4 logic cells together with hierarchical routing networks for optimum performance and power consumption
    • Each logic cell can be used as two separate 4-input LUTs or one 5-input LUT.
    • Direct input selection to the register allows combinatorial and sequential logic to be used separately.
    • Multiple outputs per logic cell are strategically selected to either feedback within the same SLC or to travel out to another SLC. A shared register clock, set, and reset signals for all four logic cells helps reduce routing congestion.
  • Array sizes ranging from 8×8 SLC up to 64×64 SLC (6 metal layers)

ArcticPro 2 – GLOBAL FOUNDRIES 22nm FD-SOI

Foundry Device Type Array Sizes # of SLC$$ # Flip Flop&& # Interface signals
GF HVT+RVT 32×32 1002 SLC 4008 (LC)
192 (IO)
64+896 (A2F%)
128+1920 (F2A%)
704 (Def)
24×16 378 SLC 1512 (LC)
120 (IO)
40+560 (A2F%)
80+1200 (F2A%)
440 (Def)
40×32 1258 SLC 5032 (LC)
216 (IO)
72+1008 (A2F%)
144+2160 (F2A%)
792 (Def)

$$One SLC is equivalent to 8 LUT4 + 4 registers
&&22LC + PREIO register paths
%(reg) + (combinatorial)
*Based on APB 40MHz clock