Aurora Software Tool Suite for eFPGA Design

Device Creation Flow

Using the device creation flow, the designer can choose the size of eFPGA that needs to be embedded in their ASIC. Aurora then facilitates configuration of the I/Os so that the connections with the ASIC side can be easily decided.

Integration with Mentor Graphics Precision

QuickLogic is an OEM partner with Mentor Graphics Precision for the eFPGA synthesis solution. Mentor Graphics Precision is enhanced to support QuickLogic’s ArcticPro and ArcticPro2 architectures, and generates an optimal netlist by considering the architecture details of the device, which is very important for implementation flow.

Implementation Flow

The netlist generated by Mentor Graphics Precision is imported in Aurora, through which the designer runs the implementation flow. Tools such as Logic Optimizer, Placer and Router, which are extremely important to meeting the performance requirements of the eFPGA, are optimized for better quality of results. eFPGA requires a combination of high performance and efficient area utilization and our P&R tools with their efficient Algorithms cater well to these critical eFPGA requirements.

Physical Viewer and Enhanced GUI

Aurora’s Enhanced GUI makes it easy for designers to debug and understand more about the design and its placement, routability and more. Aurora’s Physical Viewer provides ease of use options to the eFPGA user, which makes it easier to understand how the design is being mapped to the eFPGA fabric.

Snapshot of Aurora:

STA and Power Analysis

Aurora’s STA and Power Analysis tools provide timing and power information for the design. STA tool allows the user to navigate through various timing paths which the user can optimize for better timing.

Simulation

Aurora generates Post layout files which can be used to verify the functionality with any industry standard Simulator such as Questa, Active-HDL, NC-Sim and VCS.

Borealis eFPGA Compiler

The eFPGA needs to be integrated with an ASIC. Using Borealis eFPGA compiler, the following data is generated, which is important for ASIC integration and for timing closure.

1. Netlist in CDL, v
2. ASIC .lib file generation
3. LEF and GDS for ASIC integration

eFPGA Design Flow: